/r/FPGA

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Is this course solid?

6 upvotes • Kelbrxn_

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i am doing static timing analysis using openSTA, and i got certain violations at some corners.Can somebody suggest me some ways to remove these violations

5 upvotes • Guptasanchit

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I'm trying to implement a 10gb eth mac core into my virtex-6. Confused on what to constrain.

5 upvotes • Ex_Ho

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Vivado Software version

5 upvotes • Squiiddy_

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Alternatives to compiler directives for multiple configurations?

5 upvotes • Bubbly_Chemist1872

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Cool project ideas?

5 upvotes • andisann

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Practice Resources for VHDL and Verilog

5 upvotes • ElecSloth

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Yosys vs Synopsys Design Compiler for Senior Design Project

5 upvotes • codywallopson

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Multi bitstream configuration for zynq ultrascale+

5 upvotes • BenjDis

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Beginner (Basys3) quick questions

5 upvotes • Fetaostcoder

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Title	Upvotes	Author	Mark as read	Favorited	Rating	Add to a list
Is this course solid?	6	Kelbrxn_
i am doing static timing analysis using openSTA, and i got certain violations at some corners.Can somebody suggest me some ways to remove these violations	5	Guptasanchit
I'm trying to implement a 10gb eth mac core into my virtex-6. Confused on what to constrain.	5	Ex_Ho
Vivado Software version	5	Squiiddy_
Alternatives to compiler directives for multiple configurations?	5	Bubbly_Chemist1872
Cool project ideas?	5	andisann
Practice Resources for VHDL and Verilog	5	ElecSloth
Yosys vs Synopsys Design Compiler for Senior Design Project	5	codywallopson
Multi bitstream configuration for zynq ultrascale+	5	BenjDis
Beginner (Basys3) quick questions	5	Fetaostcoder