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/u/ehb64's
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/r/FPGA
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2024
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Interfacing a fast FPGA with slow/async SRAM
8 upvotes
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A few style questions: negative edges, explicit widths, and always_comb/always_ff
3 upvotes
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Interfacing a fast FPGA with slow/async SRAM
8
--
10
9
8
7
6
5
4
3
2
1
0
A few style questions: negative edges, explicit widths, and always_comb/always_ff
3
--
10
9
8
7
6
5
4
3
2
1
0
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